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FEATURES
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LTC3602 2.5A, 10V, Monolithic Synchronous Step-Down Regulator DESCRIPTION
The LTC(R)3602 is a high efficiency, monolithic synchronous, step-down DC/DC converter utilizing a constant-frequency, current mode architecture. It operates from an input voltage range of 4.5V to 10V and provides an adjustable regulated output voltage from 0.6V to 9.5V while delivering up to 2.5A of output current. The internal synchronous power switch with 65m on-resistance increases efficiency and eliminates the need for an external Schottky diode. The switching frequency can either be set by an external resistor or synchronized to an external clock. OPTI-LOOP(R) compensation allows the transient response to be optimized over a wide range of loads and output capacitors. The LTC3602 can be configured for either Burst Mode operation or forced continuous operation. Forced continuous operation reduces noise and RF interference, while Burst Mode operation provides the high efficiency at light loads. In Burst Mode operation, external control of the burst clamp level allows the output voltage ripple to be adjusted according to the requirements of the application.
, LT, LTC, LTM, Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
Wide Input Voltage Range: 4.5V to 10V 2.5A Output Current Low RDS(ON) Internal Switches: 65m and 90m Programmable Frequency: 300kHz to 3MHz Low Quiescent Current: 75A 0.6V 1% Reference Allows Low Output Voltage 99% Maximum Duty Cycle Adjustable Burst Mode(R) Clamp Synchronizable to External Clock Power Good Output Voltage Monitor Overtemperature Protection Available in 16-Lead Exposed TSSOP and 4mm x 4mm QFN Packages
APPLICATIONS
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Point-of-Load Supplies Portable Instruments Server Backplane Power Battery-Powered Devices
TYPICAL APPLICATION
3.3V, 2.5A, 1MHz Step-Down Regulator
VIN 4.5V TO 10V 22F RUN RT 105k 2.2H PGOOD TRACK/SS 4.32k ITH 1nF SYNC/MODE VFB PGND 475k 22pF
3602 TA01
Efficiency and Power Loss vs Load Current
100 95 VIN = 7V EFFICIENCY 1000 POWER LOSS 80 75 70 65 60 0.01 0.1 1 LOAD CURRENT (A) 1 10
3602 TA01b
10000
PVIN
INTVCC BOOST 0.22F
1F EFFICIENCY (%)
90 85
POWER LOSS (mW)
100
LTC3602
SW 100F
VOUT 3.3V 2.5A
10
105k
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LTC3602 ABSOLUTE MAXIMUM RATINGS
(Note 1)
Input Supply Voltage (PVIN) ....................... -0.3V to 11V SW (DC)...................................... -0.3V to (PVIN + 0.3V) BOOST ................................. (VSW -0.3V) to (VSW + 6V) RUN ........................................................... -0.3V to 11V All Other Pins ............................................... -0.3V to 6V
Peak SW Sink and Source Current (Note 7) .............6.5A Operating Temperature Range (Note 2)....-40C to 85C Junction Temperature (Notes 5, 6)........................ 125C Lead Temperature (Soldering, FE Package 10 seconds)................. 300C
PIN CONFIGURATION
BOOST TOP VIEW SW SW SW SW 15 PGND 14 PGND 21 13 PGND 12 PGND 11 TRACK/SS 6 RT 7 ITH 8 VFB 9 10 SGND RUN TOP VIEW SYNC/MODE PGOOD RT ITH VFB RUN TRACK/SS PGND 1 2 3 4 5 6 7 8 17 16 INTVCC 15 PVIN 14 BOOST 13 SW 12 SW 11 SW 10 PGND 9 PGND PVIN 1 PVIN 2 INTVCC 3 SYNC/MODE 4 PGOOD 5 20 19 18 17 16
FE PACKAGE 16-LEAD PLASTIC TSSOP
TJMAX = 125C, JA = 38C/W, JC = 10C/W EXPOSED PAD (PIN 17) IS SGND, MUST BE SOLDERED TO PCB
UF PACKAGE 20-LEAD (4mm 4mm) PLASTIC QFN
TJMAX = 125C, JA = 37C/W, JC = 10C/W EXPOSED PAD (PIN 21) IS SGND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH LTC3602EFE#PBF LTC3602IFE#PBF LTC3602EUF#PBF LTC3602IUF#PBF TAPE AND REEL LTC3602EFE#TRPBF LTC3602IFE#TRPBF LTC3602EUF#TRPBF LTC3602IUF#TRPBF PART MARKING* 3602FE 3602FE 3602 3602 PACKAGE DESCRIPTION 16-Lead Plastic TSSOP 16-Lead Plastic TSSOP 20-Lead (4mm x 4mm) Plastic QFN 20-Lead (4mm x 4mm) Plastic QFN TEMPERATURE RANGE -40C to 85C -40C to 85C -40C to 85C -40C to 85C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
SYMBOL PVIN VFB VFB(LINEREG) VFB(LOADREG) PARAMETER Operating Voltage Range Regulated Feedback Voltage Feedback Voltage Line Regulation Feedback Voltage Load Regulation
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 8.4V unless otherwise specified.
CONDITIONS ITH = 0.7V (Note 3) VIN = 5V to 10V, ITH = 0.7V ITH = 0.36V to 0.84V
l l
MIN 4.5 0.594
TYP 0.6 0.005 0.02
MAX 10 0.606 0.1
UNITS V V %/V %
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LTC3602 ELECTRICAL CHARACTERISTICS
SYMBOL VPGOOD RPGOOD IFB gm IS PARAMETER Power Good Range Power Good Resistance FB Input Bias Current Transconductance Amplifier gm Supply Current Active Mode Sleep Mode Shutdown VCC LDO Output Voltage Minimum Controllable ON-Time RUN Pin ON Threshold TRACK/SS Pull-Up Current Oscillator Frequency SYNC Capture Range Top Switch On-Resistance Bottom Switch On-Resistance Peak Current Limit Switch Leakage Current INTVCC Undervoltage Lockout INTVCC Undervoltage Lockout Hysteresis INTVCC Ramping Up 4.1 3.8 RT = 105k 0.8 0.3 90 67 4.5 0.1 4.2 700 5.2 1 4.3 VRUN Rising
l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 8.4V unless otherwise specified.
CONDITIONS MIN TYP 10 11 10 1.7 (Note 4) 500 75 0.2 4.8 0.4 5 90 0.7 1.25 1 1.2 3 1 700 100 1 5.2 A A A V ns V A MHz MHz m m A A V mV MAX 12 18 UNITS % nA ms
INTVCC tON, MIN VRUN ITRACK/SS fOSC fSYNC RDS(ON) ILIM ILSW VUVLO VUVLO, HYS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3602E is guaranteed to meet performance specifications from 0C to 85C. Specifications over the -40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: The LTC3602 is tested in a feedback loop that adjusts VFB to achieve a specified error amplifier output voltage (ITH).
Note 4: Dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. Note 5: TJ is calculated from the ambient temperature TA and the power dissipation as follows: TJ = TA + (PD)(JA C/W). Note 6: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 7: This limit indicates the current density limitations of the internal metallization and it is not tested in production.
TYPICAL PERFORMANCE CHARACTERISTICS
Burst Mode Operation
VIN = 7V VOUT = 3.3V LOAD = 50mA OUTPUT VOLTAGE 50mV/DIV OUTPUT VOLTAGE 100mV/DIV
Load Step Transient Forced Continuous
VIN = 7V VOUT = 3.3V
INDUCTOR CURRENT 500mA/DIV 10s/DIV
3602 G01
LOAD CURRENT 1A/DIV 10s/DIV
3602 G02
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LTC3602 TYPICAL PERFORMANCE CHARACTERISTICS
VREF vs Temperature
0.6008 0.6006 RESISTANCE (m) 0.6004 VREF (V) 0.6002 0.6000 0.5998 0.5996 -50 -25 95 VIN = 8.4V 90 85 80 75 70 65 60 50 25 75 0 TEMPERATURE (C) 100 125 4 5 6 8 7 INPUT VOLTAGE (V) 9 10
3602 G04
Switch On-Resistance vs Input Voltage
VBOOST - VSW = INTVCC TOP RESISTANCE (m) 140 120 100 80 60 40 20
Switch On-Resistance vs Temperature
VIN = 8.4V
TOP BOTTOM
BOTTOM
0 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
3602 G03
3602 G05
PVIN Leakage Current vs Input Voltage
7 6 INPUT CURRENT (nA) FREQUENCY (kHz) 5 4 3 2 1 0 4 5 7 6 8 INPUT VOLTAGE (V) 9 10
3602 G06
Frequency vs ROSC
3500 3000 FREQUENCY (kHz) 2500 2000 1500 1000 500 0 0 50 100 150 200 ROSC (k) 250 300 350 1020 1015 1010 1005
Frequency vs Input Voltage
ROSC = 105k
VRUN = 0V
1000 995 990 985 980 4 5 6 7 INPUT VOLTAGE (V) 8 9
3602 G08
3602 G07
Frequency vs Temperature
1020 1015 QUIESCENT CURRENT (A) 1010 FREQUENCY (kHz) 1005 ROSC = 105k 600 500 400 300 200 100 0 0 25 50 75 100 125
Quiescent Current vs Input Voltage
600 ACTIVE QUIESCENT CURRENT (A) 500 400 300 200 100
Quiescent Current vs Temperature
ACTIVE
1000 995 990 985 980 -50 -25
SLEEP
SLEEP
4
5
TEMPERATURE (C)
3602 G09
6 7 8 INPUT VOLTAGE (V)
9
10
3602 G10
0 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
3602 G11
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LTC3602 TYPICAL PERFORMANCE CHARACTERISTICS
Minimum Peak Inductor Current vs Burst Clamp Voltage
3.0 2.5 2.0 1.5 1.0 0.5 0 0.4 5
Maximum Peak Inductor Current vs Duty Cycle
100 95 EFFICIENCY (%) 90 85 80 75
Efficiency vs Load Current, Burst Mode Operation
FIGURE 6 CIRCUIT VIN = 5V VIN = 9V
PEAK INDUCTOR CURRENT (A)
PEAK INDUCTOR CURRENT (A)
4
3
2
1
0.7 0.9 0.5 0.6 0.8 BURST CLAMP VOLTAGE (V)
1.0
3602 G12
0
0
10 20 30 40 50 60 70 80 90 100 DUTY CYCLE (%)
3602 G13
70 0.01
0.1 1 LOAD CURRENT (A)
10
3602 G14
Efficiency vs Load Current, Forced Continuous
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.01 70 0.1 1 LOAD CURRENT (A) 10
3602 G15
Efficiency vs Input Voltage
100 FIGURE 6 CIRCUIT 95 ILOAD = 1A EFFICIENCY (%) ILOAD = 2.5A 100 98 96 EFFICIENCY (%) 90 85 80 75 94 92
Efficiency vs Frequency
FIGURE 6 CIRCUIT VIN = 7V ILOAD = 1A
FIGURE 6 CIRCUIT
VIN = 5V
2.2H
VIN = 9V
1H 90 88 86 84 4.7H
4
5
7 6 8 INPUT VOLTAGE (V)
9
10
3602 G16
0
500
1000 1500 2000 FREQUENCY (kHz)
2500
3000
3602 G17
Load Regulation
0.10 FIGURE 6 CIRCUIT VIN = 7V LDO OUTPUT VOLTAGE (V) 5.10 5.08
5V LDO Output Voltage vs Temperature
1.40 1.35 TRACK/SS CURRENT (A) 1.30 1.25 1.20 1.15
TRACK/SS Current vs Temperature
5.06 5.04 5.02 5.00 4.98 4.96 4.94 4.92
VOUT /VOUT (%)
0.00
-0.10
-0.20 0 0.5 1 1.5 2 LOAD CURRENT (A) 2.5
3602 G18
3
4.90 -50
-25
50 25 0 75 TEMPERATURE ( C)
100
125
1.10 -50
-25
50 25 0 75 TEMPERATURE ( C)
100
125
3602 G19
3602 G20
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LTC3602 PIN FUNCTIONS
FE/UF Package
SYNC/MODE (Pin 1/Pin 4): Mode Select and External Clock Synchronization Input. PGOOD (Pin 2/Pin 5): Power Good Output. Open-drain logic output that is pulled to ground when the output voltage is not within 10% of regulation point. RT (Pin 3/Pin 6): Frequency Set Pin. ITH (Pin 4/Pin 7): Error Amplifier Compensation Point. VFB (Pin 5/Pin 8): Feedback Pin. SGND (Pin 17/Pin 9, Pin 21): Signal Ground. RUN (Pin 6/Pin 10): Run Control Input. This pin may be tied to PVIN to enable the chip. TRACK/SS (Pin 7/Pin 11): Tracking Input for the Controller or Optional External Soft-Start Input. This pin allows the start-up of VOUT to "track" the external voltage at this pin using an external resistor divider. An external soft-start can
be programmed by connecting a capacitor between this pin and ground. Leave this pin floating to use the internal 1ms soft-start clamp. Do not tie this pin to INTVCC or to PVIN. PGND (Pins 8, 9, 10/Pins 12, 13, 14, 15): Power Ground. SW (Pins 11, 12, 13/Pins 16, 17, 18, 19): Switch Node Connection to the Inductor. BOOST (Pin 14/Pin 20): Bootstrapped Supply to the Top Side Floating Gate Driver. PVIN (Pin 15/Pins 1,2): Power Input Supply. Decouple this pin with a capacitor to PGND INTVCC (Pin 16/Pin 3): Output of Internal 5V LDO. Exposed Pad (Pin 17/Pin 21): SGND. Exposed pad is signal ground and must be soldered to the PCB.
BLOCK DIAGRAM
ITH 1A 0.6V VOLTAGE REFERENCE SLOPE COMPENSATION RECOVERY TRACK/SS 1ms SOFT-START BCLAMP
LDO
BOOST
INTVCC
PVIN
VFB
+ + + -
ERROR AMPLIFIER
+ +
BURST COMPARATOR MAIN I-COMPARATOR
-
SYNC/MODE 0.54V
- + -
OSILLATOR SLOPE COMPENSATION
SW
+ -
SW
+
0.66V
OVER-CURRENT COMPARATOR
+ -
SW
-
LOGIC REVERSE COMPARATOR
PGND
PGOOD
+ -
PGND
PGND
RT
RUN
SYNC/MODE
3602 BD
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LTC3602 OPERATION
Main Control Loop The LTC3602 is a monolithic, constant-frequency, currentmode step-down DC/DC converter. During normal operation, the internal top power switch (N-channel MOSFET) is turned on at the beginning of each clock cycle. Current in the inductor increases until the current comparator trips and turns off the top power MOSFET. The peak inductor current at which the current comparator shuts off the top power switch is controlled by the voltage on the ITH pin. The error amplifier adjusts the voltage on the ITH pin by comparing the feedback signal from a resistor divider on the VFB pin with an internal 0.6V reference. When the load current increases, it causes a reduction in the feedback voltage relative to the reference. The error amplifier raises the ITH voltage until the average inductor current matches the new load current. When the top power MOSFET shuts off, the synchronous power switch (N-channel MOSFET) turns on until either the bottom current limit is reached or the beginning of the next clock cycle. The bottom current limit is set at -2.5A for forced continuous mode and 0A for Burst Mode operation. The operating frequency is externally set by an external resistor connected between the RT pin and ground. The practical switching frequency can range from 300kHz to 3MHz. Overvoltage and undervoltage comparators will pull the PGOOD output low if the output voltage comes out of regulation by 7.5%. In an overvoltage condition, the top power MOSFET is turned off and the bottom power MOSFET is switched on until either the overvoltage condition clears or the bottom MOSFET's current limit is reached. Forced Continuous Mode Connecting the SYNC/MODE pin to INTVCC will disable Burst Mode operation and force continuous current operation. At light loads, forced continuous mode operation is less efficient than Burst Mode operation, but may be desirable in some applications where it is necessary to keep switching harmonics out of a signal band. The output voltage ripple is minimized in this mode. Burst Mode Operation Connecting the SYNC/MODE pin to a voltage in the range of 0.42V to 1V enables Burst Mode operation. In Burst Mode operation, the internal power MOSFETs operate intermittently at light loads. This increases efficiency by minimizing switching losses. During Burst Mode operation, the minimum peak inductor current is externally set by the voltage on the SYNC/MODE pin and the voltage on the ITH pin is monitored by the burst comparator to determine when sleep mode is enabled and disabled. When the average inductor current is greater than the load current, the voltage on the ITH pin drops. As the ITH voltage falls below 330mV, the burst comparator trips and enables sleep mode. During sleep mode, the top power MOSFET is held off and the ITH pin is disconnected from the output of the error amplifier. The majority of the internal circuitry is also turned off to reduce the quiescent current to 75A while the load current is solely supplied by the output capacitor. When the output voltage drops, the ITH pin is reconnected to the output of the error amplifier and the top power MOSFET along with all the internal circuitry is switched back on. This process repeats at a rate that is dependent on the load demand. Pulse-skipping operation is implemented by connecting the SYNC/MODE pin to ground. This forces the burst clamp level to be at 0V. As the load current decreases, the peak inductor current will be determined by the voltage on the ITH pin until the ITH voltage drops below 330mV. At this point, the peak inductor current is determined by the minimum on-time of the current comparator. If the load demand is less than the average of the minimum on-time inductor current, switching cycles will be skipped to keep the output voltage in regulation. Frequency Synchronization The internal oscillator of the LTC3602 can be synchronized to an external clock connected to the SYNC/MODE pin. The frequency of the external clock can be in the range of 300kHz to 3MHz. For this application, the oscillator timing resistor should be chosen to correspond to a frequency that is 25% lower than the synchronization frequency. When synchronized, the LTC3602 will operate in pulseskipping mode.
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LTC3602 OPERATION
Dropout Operation When the input supply voltage decreases toward the output voltage, the duty cycle increases toward the maximum on-time. Further reduction of the supply voltage forces the top switch to remain on for more than one cycle until it attempts to stay on continuously. In order to replenish the voltage on the floating BOOST supply capacitor, however, the top switch is forced off and the bottom switch is forced on for approximately 85ns every sixteen clock cycles. This achieves an effective duty cycle that can exceed 99%. The output voltage will then be primarily determined by the input voltage minus the voltage drop across the upper internal N-channel MOSFET and the inductor. Slope Compensation and Inductor Peak Current Slope compensation provides stability in constant-frequency architectures by preventing subharmonic oscillations at duty cycles greater than 50%. It is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 30%. Normally, the maximum inductor peak current is reduced when slope compensation is added. In the LTC3602, however, slope compensation recovery is implemented to reduce the variation of the maximum inductor peak current (and therefore the maximum available output current) over the range of duty cycles. Short-Circuit Protection When the output is shorted to ground, the inductor current decays very slowly during a single switching cycle. To prevent current runaway from occurring, a secondary current limit is imposed on the inductor current. If the inductor valley current increases to more than 4.5A, the top power MOSFET will be held off and switching cycles will be skipped until the inductor current is reduced. Overtemperature Protection When using the LTC3602 in an application circuit, care must be taken not to exceed any of the ratings specified in the Absolute Maximum Ratings section. As an added safeguard, however, the LTC3602 does incorporate an overtemperature shutdown feature. If the junction temperature reaches approximately 150C, both power switches will be turned off and the SW node will become high impedance. After the part has cooled to below 115C, it will restart. Voltage Tracking and Soft-Start Some microprocessors and DSP chips need two power supplies with different voltage levels. These systems often require voltage sequencing between the core power supply and the I/O power supply. Without proper sequencing, latch-up failure or excessive current draw may occur that could result in damage to the processor's I/O ports or the I/O ports of a supporting system device such as memory, an FPGA or a data converter. To ensure that the I/O loads are not driven until the core voltage is properly biased, tracking of the core supply and the I/O supply voltage is necessary. Voltage tracking is enabled by applying a ramp voltage to the TRACK/SS pin. When the voltage on the TRACK pin is below 0.6V, the feedback voltage will regulate to this tracking voltage. When the tracking voltage exceeds 0.6V, tracking is disabled and the feedback voltage will regulate to the internal reference voltage. The TRACK/SS pin is also used to implement an external soft-start function. A 1.2A current is sourced from this pin so that an external capacitor may be added to create a smooth ramp. If this ramp is slower than the internal 1ms soft-start, then the output voltage will track this ramp during start up instead. Leave this pin floating to use the internal 1ms soft-start ramp. Do not tie the TRACK/SS pin to INTVCC or to PVIN.
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LTC3602 APPLICATIONS INFORMATION
The basic LTC3602 application circuit is shown on the front page of this data sheet. External component selection is determined by the maximum load current and begins with the selection of the inductor value and operating frequency followed by CIN and COUT. Operating Frequency Selection of the operating frequency is a tradeoff between efficiency and component size. High frequency operation allows the use of smaller inductor and capacitor values. Operation at lower frequencies improves efficiency by reducing internal gate charge and switching losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. The operating frequency of the LTC3602 is determined by an external resistor that is connected between the RT pin and ground. The value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator and can be calculated by using the following equation: R OSC = 1.15 * 1011 - 10k f(Hz) A reasonable starting point for selecting the ripple current is IL = 0.4(IMAX), where IMAX is the maximum output current. The largest ripple current occurs at the highest VIN. To guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation: V V OUT * 1- OUT L= fIL(MAX) VIN(MAX) The inductor value will also have an effect on Burst Mode operation. The transition from low current operation begins when the peak inductor current falls below a level set by the burst clamp. Lower inductor values result in higher ripple current which causes this to occur at lower load currents. This causes a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to increase. Inductor Core Selection Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of the more expensive ferrite cores. Actual core loss is independent of core size for a fixed inductor value but it is very dependent on the inductance selected. As the inductance increases, core losses decrease. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates "hard," which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Different core materials and shapes will change the size/current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and do not radiate energy but generally cost more than powdered iron core inductors with similar
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Although frequencies as high as 3MHz are possible, the minimum on-time of the LTC3602 imposes a minimum limit on the operating duty cycle. The minimum on-time is typically 90ns. Therefore, the minimum duty cycle is equal to 100 * 90ns * f(Hz). Inductor Selection For a given input and output voltage, the inductor value and operating frequency determine the ripple current. The ripple current IL increases with higher VIN and decreases with higher inductance. V V IL = OUT * 1- OUT fL VIN Having a lower ripple current reduces the ESR losses in the output capacitors and the output voltage ripple. Highest efficiency operation is achieved at low frequency with small ripple current. This, however, requires a large inductor.
9
LTC3602 APPLICATIONS INFORMATION
characteristics. The choice of which style inductor to use mainly depends on the price vs size requirements and any radiated field/EMI requirements. New designs for surface mount inductors are available from Coiltronics, Coilcraft, Toko and Sumida. CIN and COUT Selection The input capacitance, CIN, is needed to filter the trapezoidal current at the source of the top MOSFET. To prevent large ripple voltage, a low ESR input capacitor sized for the maximum RMS current should be used. RMS current is given by: IRMS = IOUT(MAX ) * VOUT * VIN VIN -1 VOUT density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing. Using Ceramic Input and Output Capacitors Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. However, care must be taken when these capacitors are used at the input and output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part. Output Voltage Programming The output voltage is set by an external resistive divider according to the following equation: R2 VOUT = 0.6V * 1+ R1 The resistive divider allows the VFB pin to sense a fraction of the output voltage as shown in Figure 1.
VOUT R2 VFB LTC3602 SGND
3602 F01
This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. The selection of COUT is determined by the effective series resistance (ESR) that is required to minimize voltage ripple and load step transients, as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response as described in a later section. The output ripple, VOUT, is determined by: 1 VOUT IL * ESR + 8fCOUT The output ripple is highest at maximum input voltage since IL increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance
R1
Figure 1. Setting the Output Voltage
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LTC3602 APPLICATIONS INFORMATION
Burst Clamp Programming If the voltage on the SYNC/MODE pin is less than INTVCC by 1V or more, Burst Mode operation is enabled. During Burst Mode operation, the voltage on the SYNC/MODE pin determines the burst clamp level. This level sets the minimum peak inductor current, IBURST, for each switching cycle according to the following equation: + 0.42V 6A / V VBURST is the voltage on the SYNC/MODE pin. IBURST can be programmed in the range of 0A to 3.5A, which corresponds to a VBURST range of 0.42V to 1V. As the output load current drops, the peak inductor current decreases to keep the output voltage in regulation. When the output load current demands a peak inductor current that is less than IBURST, the burst clamp will force the peak inductor current to remain equal to IBURST regardless of further reductions in the load current. Since the average inductor current is therefore greater than the output load current, the voltage on the ITH pin will decrease. When the ITH voltage drops to 330mV, sleep mode is enabled in which both power MOSFETs are shut off along with most of the circuitry to minimize power consumption. All circuitry is turned back on and the power MOSFETs begin switching again when the output voltage drops out of regulation. The value for IBURST is determined by the desired amount of output voltage ripple. As the value of IBURST increases, the sleep time between pulses and the output voltage ripple increases. The burst clamp voltage, VBURST, can be set by a resistor divider from the INTVCC pin. Alternatively, the SYNC/MODE pin may be tied directly to the VFB pin to set VBURST = 0.6V (IBURST = 1A), or through an additional divider resistor (R3) to set VBURST = 0.46V to 0.6V (see Figure 2).
INTVCC LTC3602 SYNC/MODE R1 SGND SGND
3602 F02
VBURST =
IBURST
Pulse-skipping, which is a compromise between low output voltage ripple and efficiency, can be implemented by connecting the SYNC/MODE pin to ground. This sets IBURST to 0A. In this condition, the peak inductor current is limited by the minimum on-time of the current comparator and the lowest output voltage ripple is achieved while still operating discontinuously. During very light output loads, pulse-skipping allows only a few switching cycles to be skipped while maintaining the output voltage in regulation. Frequency Synchronization The LTC3602's internal oscillator can be synchronized to an external clock signal. During synchronization, the top MOSFET turn-on is locked to the falling edge of the external frequency source. The synchronization frequency range is 300kHz to 3MHz. Synchronization only occurs if the external frequency is greater than the frequency set by the RT resistor. Because slope compensation is generated by the oscillator's internal ramp, the external frequency should be set 25% higher than the frequency set by the RT resistor to ensure that adequate slope compensation is present. When synchronized, the LTC3602 will operate in pulse-skipping mode. INTVCC Regulator The LTC3602 features an integrated P-channel low dropout linear regulator (LDO) that supplies power to the INTVCC supply pin from the PVIN pin. This LDO supply has been designed to deliver up to 35mA of load current for the powering of the internal gate drivers and other internal circuitry. A small external load may also be applied provided that the total current from the INTVCC supply does not exceed 35mA. The INTVCC pin should be bypassed with no less than a 0.22F ceramic capacitor. A 1F ceramic capacitor is suitable for most applications.
R2 FB VOUT R3 (OPTIONAL)
R2
LTC3602 SYNC/MODE
R1
VBURST = 0.46V TO 1V
VBURST = 0.46V TO 0.6V
Figure 2. Programing the Burst Clamp
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11
LTC3602 APPLICATIONS INFORMATION
Topside MOSFET Driver Supply (BOOST Pin) The LTC3602 uses a bootstrapped supply to power the gate of the internal topside MOSFET (Figure 3). When the topside MOSFET is off and the SW pin is low, diode DBST charges capacitor CBST to the voltage on the INTVCC supply. In order to turn on the topside MOSFET, the voltage on the BOOST pin is then applied to its gate. As the topside MOSFET turns on, the SW pin rises to the PVIN voltage and the BOOST pin rises to PVIN + INTVCC, thereby keeping the MOSFET fully enhanced. For most applications, a 0.22F ceramic capacitor is appropriate for CBST. Schottky diode DBST should have a reverse breakdown voltage that is greater than PVIN(MAX).
INTVCC LTC3602 BOOST CBST SW
3602 F03
voltage of the converter. To use the default, internal 1ms soft-start ramp, leave the TRACK/SS pin floating. Do not tie the TRACK/SS pin to INTVCC or to PVIN. To increase the soft-start time above 1ms, place a cap on the TRACK/SS pin. A 1.2A internal pull-up current will charge this cap, resulting in a soft-start ramp time given by: t SS = CSS * 0.6 1.2A
When the LTC3602 detects a fault condition (either undervoltage lockout or overtemperature), the TRACK/SS pin is quickly pulled to ground and the internal soft-start timer is also reset. This ensures an orderly restart when using an external soft-start capacitor. To implement tracking, a resistor divider is placed between an external supply (VX) and the TRACK/SS pin as shown in Figure 5a. This technique can be used to cause VOUT to ratiometrically track the VX supply (Figure 5b), according to the following: VOUT RTA RA + RB = * VX RA RTA + RTB For coincident tracking, as shown in Figure 5c, (VOUT = VX during start-up), RTA = RA, RTB = RB Note that the 1.2A current that is sourced from the TRACK/SS pin will cause a slight offset in the voltage seen on the TRACK/SS pin and consequently on the VOUT voltage during tracking. This VOUT offset due to the TRACK/SS current is given by: VOS,TRK = (1.2A) * RTARTA RA +RB * RTA +RTB RA
DBST CINTVCC
Figure 3. Topside MOSFET Supply
Run and Soft-Start/Tracking Functions The LTC3602 has a low power shutdown mode which is controlled by the RUN pin. Pulling the RUN pin below 0.7V puts the LTC3602 into a low quiescent current shutdown mode (IQ < 1A). When the RUN pin is greater than 0.7V, the controller is enabled. The RUN pin can be driven directly from logic as shown in Figure 4. Soft-start and tracking are implemented by limiting the effective reference voltage as seen by the error amplifier. Ramping up the effective reference into the error amp in turn causes a smooth and controlled ramp on the output
3.3V OR 5V LTC3602 RUN PVIN 4.7M LTC3602 RUN
3602 F04
For most applications, this offset is small and has minimal effect on tracking performance. For improved tracking accuracy, reduce the parallel impedance of RTA and RTB.
Figure 4. RUN Pin Interfacing
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12
LTC3602 APPLICATIONS INFORMATION
VOUT VX VFB RTB LTC3602 TRACK/SS RTA
3602 F05a
RB
The VIN operating current loss dominates the efficiency loss at very low load currents whereas the I2R loss dominates the efficiency loss at medium to high load currents. 1. The VIN operating current comprises three components: The DC Supply Current as given in the electrical characteristics, the internal MOSFET gate charge currents and the internal topside MOSFET transition losses. The MOSFET gate charge current results from switching the gate capacitance of the internal power MOSFET switches. The gates of these switches are driven from the INTVCC supply. Each time the gate is switched from high to low to high again, a packet of charge dQ moves from INTVCC to ground. The resulting dQ/dt is the current out of INTVCC that is typically larger than the DC bias current. In continuous mode, the gate charge current can be approximated by IGATECHG = f(9.5nC). Since the INTVCC voltage is generated from VIN by a linear regulator, the current that is internally drawn from the INTVCC supply can be treated as VIN current for the purposes of efficiency considerations. Transition losses apply only to the internal topside MOSFET and become more prominent at higher input voltages. Transition losses can be estimated from: Transition Loss = (1.7) VIN2 * IO(MAX) * (120pF) * f 2. I2R losses are calculated from the resistances of the internal switches, RSW and external inductor RL. In continuous mode, the average output current flowing through inductor L is "chopped" between the main switch and the synchronous switch. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 - DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses, simply add RSW to RL and multiply the result by the square of the average output current: I2R Loss = IO2(RSW + RL) Other losses, including CIN and COUT ESR dissipative losses and inductor core losses, generally account for less than 2% of the total power loss.
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RA
Figure 5a. Using the TRACK/SS Pin to Track VX
VX OUTPUT VOLTAGE
VOUT
TIME
(5b) Ratiometric Tracking
VX OUTPUT VOLTAGE
VOUT
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TIME
(5c) Coincident Tracking
Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as: Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses: VIN operating current and I2R losses.
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LTC3602 APPLICATIONS INFORMATION
Thermal Considerations In most applications, the LTC3602 does not dissipate much heat due to its high efficiency. But, in applications where the LTC3602 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 150C, both power switches will be turned off and the SW node will become high impedance. To prevent the LTC3602 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: TR = (PD) * (JA) where PD is the power dissipated by the regulator and JA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: TJ = TA + TR where TA is the ambient temperature. As an example, consider the LTC3602 in dropout at an input voltage of 8V, a load current of 2.5A and an ambient temperature of 70C. From the Typical Performance graph of Switch Resistance, the RDS(ON) of the top switch at 70C is approximately 120m. Therefore, power dissipated by the part is: PD = (ILOAD2)(RDS(ON)) = (2.5A)2(120m) = 0.75W For the TSSOP package, the JA is 38C/W. Thus the junction temperature of the regulator is: TJ = 70C + (0.75W)(38C/W) = 98.5C which is below the maximum junction temperature of 125C. ROSC = Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ILOAD*(ESR), where ESR is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT, generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. The ITH pin external components and output capacitor shown in the front page application will provide adequate compensation for most applications. Design Example As a design example, consider using the LTC3602 in an application with the following specifications: VIN = 8.4V, VOUT = 3.3V, IOUT(MAX) = 2.5A, IOUT(MIN) = 100mA, f= 1MHz. Because efficiency is important at both high and low load current, Burst Mode operation will be utilized. First, calculate the timing resistor: 1.15 * 1011 - 10k = 105k 1MHz
Next, calculate the inductor value for about 40% ripple current at maximum VIN: 3.3V 3.3V L = 1MHz 1A * 1- 8.4V = 2H )( ) ( Using a 2.2H inductor results in a maximum ripple current of: 3.3V 3.3V IL = 1MHz 2.2H * 1- 8.4V = 0.91A )( ) ( COUT will be selected based on the ESR that is required to satisfy the output voltage ripple requirement and the bulk capacitance needed for loop stability. In this application, a tantalum capacitor will be used to provide the bulk
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14
LTC3602 APPLICATIONS INFORMATION
capacitance and a ceramic capacitor in parallel to lower the total effective ESR. For this design, a 100F ceramic capacitor will be used. CIN should be sized for a maximum current rating of: IRMS = 2.5A * 3.3V 8.4V * - 1 = 1.22ARMS 8.4V 3.3V PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3602. Check the following in your layout: 1. A ground plane is recommended. If a ground plane layer is not used, the signal and power grounds should be segregated with all small signal components returning to the SGND pin at one point which is then connected to the PGND pin close to the LTC3602. 2. Connect the (+) terminal of the input capacitor(s), CIN, as close as possible to the PVIN pin. This capacitor provides the AC current into the internal power MOSFETs. 3. Keep the switching node, SW, away from all sensitive small signal nodes. 4. Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power components. You can connect the copper areas to any DC net (PVIN, INTVCC, VOUT, PGND, SGND, or any other DC rail in your system).
VIN 8.4V CIN 22F
Decoupling the PVIN pin with a 22F ceramic capacitor is adequate for most applications. The output voltage can now be programmed by choosing the values of R1 and R2. Chose R1 = 105k and calculate R2 as: VOUT R2 =R1 0.6V - 1 = 472.5k Choose a standard value of R2 = 475k. The voltage on the MODE pin will be set to 0.6V by tying the MODE pin to the FB pin. This will set the burst current equal to approximately 1A. Figure 6 shows a complete schematic for this design example.
CVCC 1F RPG 200k PGOOD ROSC 105k CITH 1nF RT RITH 4.32k ITH VFB R1 105k R2 475k CFB 22pF RUN TRACK/SS PGND LTC3602 SW SW SW PGND PGND L1 2.2H BOOST CBST 0.22F SYNC/MODE PGOOD INTVCC PVIN D1
VOUT 3.3V 2.5A COUT 100F
3602 F06
L1: VISHAY IHLP2525CZER2R2MO1 CIN: TAIYO YUDEN TMK325BJ226MM-T COUT: TDK C3225X5ROJ107M
Figure 6. 8.4V to 3.3V, 2.5A Regulator at 1MHz, Burst Mode Operation
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15
LTC3602 TYPICAL APPLICATIONS
1.8V, 2.5A Regulator at 1MHz, Burst Mode Operation
VIN 5V to 10V CIN 22F
R3 845k
RPG 200k SYNC/MODE INTVCC PVIN D1 RT RITH 4.32k ITH VFB LTC3602 SW SW SW PGND PGND BOOST
CVCC 1F
PGOOD R4 137k CITH 1nF
PGOOD ROSC 105k
CBST 0.22F
R1 105k
L1 1H
RUN TRACK/SS
VOUT 1.8V 2.5A
CFB 22pF
R2 210k
PGND
COUT 100F 2
L1: VISHAY IHLP2525CZER1R0MO1 CIN: TAIYO YUDEN TMK325BJ226MM-T COUT: TAIYO YUDEN AMK316BJ107ML
3602 TA02
Efficinecy vs Load Current
100 95 EFFICIENCY (%) 90 85 80 75 70 0.01 VIN = 5V VIN = 8.4V VIN = 10V
0.1 1 LOAD CURRENT (A)
10
3602 TA02b
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16
LTC3602 TYPICAL APPLICATIONS
3.3V, 2.5A Regulator at 2MHz, Forced Continuous, Small Size
VIN 10V CIN 22F
CVCC 1F RPG 200k PGOOD ROSC 47.5k CITH 470pF RT RITH 2.94k ITH VFB R1 105k CFB 10pF RUN TRACK/SS R2 475k PGND LTC3602 SW SW SW PGND PGND L1 1H BOOST CBST 0.22F SYNC/MODE PGOOD INTVCC PVIN D1
VOUT 3.3V 2.5A
COUT 47F
L1: VISHAY IHLP1616ABER1R0M01 CIN: TAIYO YUDEN EMK316BJ226ML-T COUT: MURATA GRM3ICR60J476ME19
3602 TA04
2.5V, 2.5A Regulator, Synchronized to 1.8MHz
1.8MHz EXT. CLK CVCC 1F RPG 200k PGOOD ROSC 69.8k CITH 470pF RITH 2.94k RT ITH VFB R1 105k RUN TRACK/SS R2 332k PGND LTC3602 BOOST CBST 0.22F SW SW SW PGND PGND COUT 100F L1 1H SYNC/MODE PGOOD INTVCC PVIN D1 VIN 8.4V CIN 22F
VOUT 2.5V 2.5A
CFB 22pF
L1: VISHAY IHLP2525CZER1R0M01 CIN: TAIYO YUDEN TMK325BJ226MM-T COUT: TDK C3225X5ROJ107M
3602 TA05
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17
LTC3602 PACKAGE DESCRIPTION
FE Package 16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BA
4.90 - 5.10* (.193 - .201) 2.74 (.108) 16 1514 13 12 1110 9
2.74 (.108)
6.60
0.10 4.50 0.10
SEE NOTE 4
2.74 (.108) 0.45 0.05 1.05 0.10 0.65 BSC 2.74 6.40 (.108) (.252) BSC
RECOMMENDED SOLDER PAD LAYOUT
12345678 1.10 (.0433) MAX
0 -8
4.30 - 4.50* (.169 - .177)
0.25 REF
0.09 - 0.20 (.0035 - .0079)
0.50 - 0.75 (.020 - .030)
0.65 (.0256) BSC
NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE
0.195 - 0.30 (.0077 - .0118) TYP
0.05 - 0.15 (.002 - .006)
FE16 (BA) TSSOP 0204
4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE
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18
LTC3602 PACKAGE DESCRIPTION
UF Package 20-Lead Plastic QFN (4mm x 4mm)
(Reference LTC DWG # 05-08-1710 Rev A)
0.70 4.50 0.05 3.10 0.05 2.00 REF 2.45 0.05 2.45 0.05
0.05
PACKAGE OUTLINE
0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.75 4.00 0.10 0.05 R = 0.05 TYP BOTTOM VIEW--EXPOSED PAD R = 0.115 TYP PIN 1 NOTCH R = 0.20 TYP OR 0.35 45 CHAMFER
19 20 0.40 1 0.10
PIN 1 TOP MARK (NOTE 6) 2.45 4.00 0.10 2.00 REF 2.45 0.10 0.10
2
(UF20) QFN 01-07 REV A
0.200 REF 0.00 - 0.05 NOTE: 1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-1)--TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.25
0.05
0.50 BSC
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC3602 RELATED PARTS
PART NUMBER LTC1877 LTC1879 LTC3404 LTC3405/LTC3405A LTC3406/LTC3406B DESCRIPTION 600mA (IOUT), 550kHz, Synchronous Step-Down DC/DC Converter 1.2A (IOUT), 550kHz, Synchronous Step-Down DC/DC Converter 600mA (IOUT), 1.4MHz, Synchronous Step-Down DC/DC Converter 300mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converter 600mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converter COMMENTS 96% Efficiency, VIN: 2.7V to 10V, VOUT(MIN) = 0.8V, IQ = 10A, ISD <1A, MS8 Package 95% Efficiency, VIN: 2.7V to 10V, VOUT(MIN) = 0.8V, IQ = 15A, ISD <1A, TTSOP-16 Package 95% Efficiency, VIN: 2.7V to 6V, VOUT(MIN) = 0.8V, IQ = 10A, ISD <1A, MS8 Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 20A, ISD <1A, ThinSOTTM Package 96% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 20A, ISD <1A, ThinSOT Package
LTC3407/LTC3407-2 Dual 600mA/810mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, Converter IQ = 40A, ISD <1A, MS10E and 3mm x 3mm DFN Packages LTC3409 LTC3411 LTC3412 LTC3413 LTC3414 LTC3416 LTC3418 LTC3430 LTC3441 LTC3533 LTC3548 LTC3610 600mA, 2.6MHz, Low (VIN) Synchronous Step-Down DC/DC Converter 1.25A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 2.5A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 1.6V to 5.5V, IQ = 65A, ISD <1A, 3mm x 3mm DFN Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60A, ISD <1A, MS10 and 3mm x 3mm DFN Packages 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60A, ISD <1A, TSSOP-16E Package
3A (IOUT Sink/Source), 2MHz, Monolithic Synchronous Regulator for 90% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = VREF/2, DDR/QDR Memory Termination IQ = 280A, ISD <1A, TSSOP-16E Package 4A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 4A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 8A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 60V, 2.75A (IOUT), 200kHz, High Efficiency Step-Down DC/DC Converter 1.2A (IOUT), 1MHz, Synchronous Buck-Boost DC/DC Converter 2A, 2MHz, Wide Input Voltage Synchronous Buck-Boost DC/DC Converter 400mA/800mA Dual Synchronous Buck-Boost DC/DC Converter 12A, 24V, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 64A, ISD <1A, TSSOP-20E Package 95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 64A, ISD <1A, TSSOP-20E Package 95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 380A, ISD <1A, QFN Package 90% Efficiency, VIN: 5.5V to 60V, VOUT(MIN) = 1.2V, IQ = 2.5mA, ISD = 25A, TSSOP-16E Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT: 2.5V to 5.5V, IQ = 25A, ISD <1A, DFN Package 96% Efficiency, VIN: 1.8V to 5.5V, IQ = 40A, ISD <1A, 3mm x 4mm DFN Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40A, ISD <1A, MS8E and DFN Packages 95% Efficiency, VIN: 4V to 24V, VOUT(MIN) = 0.6V, Fast Transient Response, IQ = 900A, ISD <15A, 9mm x 9mm QFN Package VIN: 4V to 32V, Fast Transient Response, IQ = 900A, ISD <15A, 9mm x 9mm QFN Package
LTC3611
10A, 36V, Synchronous Step-Down DC/DC Converter
ThinSOT is a trademark of Linear Technology Corporation.
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20 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 0408 REV B * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2008

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